This invention relates to circuit devices, and more particularly, to a method and apparatus for reducing inductive switching transients in an electrical signal.
Conventional electrical circuits inherently contain inductance. Inductance resists changes in current flow and can introduce transient voltage spikes when the current flow suddenly changes. These voltage spikes can be an order of magnitude or more greater than the voltage of the signal itself. The greater the inductance in a circuit, the more resistive it will be to changes in current flow, thereby inducing larger transient voltage spikes.
Induced transient voltages can be particularly problematic in power and ground wiring. Power and ground voltages typically are transmitted to numerous electrical components in a circuit, often through a few, relatively long wires. Generally, increasing the length of a particular wire will cause an increase in the inductance of the wire. Relatively long power and ground wires can therefore have a relatively large inductance. Sudden changes in the current consumed by a circuit that is powered by these relatively long power and ground wires can produce large voltage spikes in the wires. Because the power and ground wires are often coupled to many circuits, the induced voltage spikes can also be coupled to these many circuits.
An example of a circuit in which voltage transients are inductively generated in lines applying power to the circuit is illustrated in FIG. 1. An inverter circuit 2 is formed by a PMOS transistor 4 and an NMOS transistor 6. A source of the PMOS transistor 4 is coupled to a supply voltage V1 through a conductor 8, and a source of the NMOS transistor 6 is coupled to ground through a conductor 9. The drains of the transistors 4, 6 are coupled to each other and to one terminal of a load L. Another terminal of the load L is coupled to a voltage VT. For this example, the conductors 8, 9 are assumed to be bonding wires extending from an integrated circuit chip (not shown) to external terminals (not shown) of the integrated circuit. The ends of the conductors 8, 9 that are coupled to the circuit 2 are also coupled to other circuits (not shown) on the integrated circuit chip. As result, any voltage transients that are inductively generated by the conductors 8, 9 our coupled to these other circuits.
In operation, when the input signal IN is a logic xe2x80x9c1xe2x80x9d equal to the supply voltage V1, the NMOS transistors 6 is turned ON and the PMOS transistor 4 is turned OFF so that current flows to ground through the NMOS transistor 6 and the conductor 9. When the input signal IN is logic xe2x80x9c0xe2x80x9d equal to ground potential, the PMOS transistor 4 is turned ON and the NMOS transistor 6 is turned OFF so that current flows from the supply voltage V1 through the conductor 8 and the PMOS transistor 4.
As is known in the art, the conductors 8, 9 have a small but nevertheless significant inductance. As a result, voltages transients are generated at the sources of the transistors 4, 6, as illustrated by the waveforms VX1 and VX2 shown in FIG. 2. As shown in FIG. 2, prior to time t0, the voltage VX1 is at V1 because the PMOS transistor 4 is ON. At time t0, the input signal IN transitions high, thereby turning OFF the PMOS transistor 4 and turning ON the NMOS transistor 6. Turning OFF the PMOS transistor 4 abruptly terminates the flow of current through the conductor 8, thereby causing a positive voltage transient or spike to be generated at time t0. The voltage transient is, of course, coupled to the other circuits on the integrated circuit chip that are powered through the conductors 8, 9. The voltage transient is of a sufficient magnitude that it may very well cause these other circuits to erroneously respond to the voltage transient.
As further shown in FIG. 2, at time t1 the input signal IN goes low, thereby turning ON the PMOS transistor 4 and turning OFF the NMOS transistor 6. Turning OFF the NMOS transistor 6 abruptly terminates the flow of current through the conductor 9, thereby causing a negative voltage transient to be generated. Again, this voltage transient is coupled to the other circuits on the integrated circuit chip that are powered through the conductors 8, 9. The inductance of power lines can therefore great significant problems in high-speed digital integrated circuits.
Induced voltage transients are particularly troublesome when they are coupled to high speed circuits because high speed circuits are particularly sensitive to voltage transients.
Problems caused by induced voltage transients tend to increase with a decrease in the magnitude of supply voltages. Typically, digital circuits powered by reduced supply voltages use correspondingly reduced switching levels. As a result, these digital circuits are more susceptible to voltages transients.
One technique for making a digital circuit less susceptible to voltage transients is to raise the switching levels of switching devices used in the circuit. However, raising the switching levels in a digital circuit can create other problems. For example, raising switching levels can decrease the operating speed of a digital circuit because it requires more time for signals transitioning between logic levels to transition over a larger voltage range.
In the past, filter capacitors coupled to power and ground lines have been used to attenuate voltage transients on these lines. Although filter capacitors continue to be useful in attenuating voltage transients on power and ground lines, they may not be capable of adequately attenuating relatively large voltage transients. Furthermore, since capacitors that are large enough to filter voltage transients cannot easily and inexpensively be fabricated on integrated circuits, filter capacitors are of limited usefulness for attenuating voltage transients generated in integrated circuits.
As mentioned above, the inductance of a power line is generally proportional to its length. Reducing the lengths of power lines can therefore reduce their inductance, and thereby correspondingly decrease the magnitude of voltage transients induced in the lines. One approach to reducing the length of power lines is to use a packaging arrangement known as a xe2x80x9cBall Grid Arrayxe2x80x9d (xe2x80x9cBGAxe2x80x9d). A BGA is a grid of contacts laid out over a surface of an integrated circuit package that is placed against a surface of a printed circuit board or other substrate. The BGA contacts are coupled to similar contacts formed on the surface of the substrate, thus resulting in a relatively short signal path between the integrated circuit package and the substrate. In contrast, pins and the like formed along the edges of integrated circuit packages constitute a substantially longer short signal path between the integrated circuit package and the substrate. Furthermore, since the external contacts of a BGA are positioned beneath the integrated circuit chip, the lengths of internal lead wires extending from the chip to the external contacts are relatively short. In contrast, lead wires extending from a chip to external contact pins positioned along the periphery of an integrated circuit package are substantially longer. The use of BGAs has several drawbacks. BGAs are more difficult to mount, requiring a more elaborate layout so power leads can route through the appropriate layers and around other traces and components. This more elaborate layout also contributes to increased fabrication costs and time. Also, BGAs may not be capable of adequately reducing inductance in power and signal lines, and they are not effective in reducing the inductance of power and signal lines formed on the integrated circuit chip.
Yet another approach to reducing the inductance of power and signal lines, particularly bond wires extending between integrated circuit chips and external contacts, is to use low inductance alloys for the bond wires. The inductance of a wire decreases with the magnetic permeability of the material in the wire. Therefore a wire using an alloy having a decreased magnetic permeability will have a lower inductance than the equivalent wire made of conventional bond wire. The drawback to using low permeability alloys is that they are typically more expensive and less reliable overall than conventional bond wire.
There is therefore a need to effectively reduce the sensitivity of circuits to induced voltage transients in power and signal lines.
The present invention provides apparatus and methods for reducing switching transients induced in power or signal lines that are connected to a primary circuit. A smoothing circuit is connected to the power or signal lines in parallel with the primary circuit. The primary circuit performs a predetermined function in response to receiving at least one input signal, and, in performing that function, the current drawn by the primary circuit through the power or signal line changes. The smoothing circuit responds to the same input signal or signals by changing the current drawn by the smoothing circuit through the power or signal line in a manner that is opposite the change in current drawn by the primary circuit. As a result, the current flow through the power or signal line remains substantially constant despite substantial changes in the current drawn through the power or signal line by the primary circuit responsive to the input signal or signals.